In this paper, the design methodology for a High-Speed 8B/10B encoding architecture has been discussed. By means of the new truth table and with the help of Pass-Transistor Logic (PTL), a new structure has been designed in CMOS technology, which shows a superior Speed performance. Also, power consumption is optimized because of careful design considerations. These features, along with the simplicity of the employed circuitry are the quality of this work to be repeatedly used in High-Speed communication systems. The design process has been explained in detail so that the idea can completely be understood. Moreover, the proposed structure has been demonstrated in the circuit level for better clarification. Post-layout simulation results for TSMC 0. 18μ m standard CMOS technology depict the correct behavior of the proposed architecture whilst the power consumption is 1. 64mW from 1. 8v power supply.

This review paper contains the discussion about performance analysis of High Speed 4-2 compressor architectures, starting from the general idea; conventional form for implementation of this building block along with its truth table has been studied. Thereafter, the modified versions which show promise for High Speed multiplier implementations along with their benefits and drawbacks were demonstrated and comprehensively analyzed. Following the same principles, an optimized structure for the 4-2 compressor is obtained which has 2 XOR gate level delay for the critical path and contains the least delay among the reported works. As another advantage, because of uniform paths the output waveforms will be free of any glitches. Simulation results for TSMC 0. 18 μ m CMOS technology and 1. 8V power supply using HSPICE have been provided to show the superiority of our designed architecture in terms of the Speed performance. Finally, to confirm the correct behavior of proposed compressor, an 8x8 bit multiplier was designed which can operate at the frequency of 500MHz without employing any special multiplication algorithm for partial product generation.

In this paper, a CMOS four quadrant multiplier based on flipped voltage follower and differential squaring circuit is presented. The proposed circuit has a compact architecture which operates at a Higher Speed and a Higher input voltage range compared to the previously presented structures. The transistors operate in both saturation and ohmic regions. The circuit operates with a single supply voltage of 3.3V in a 0.35 μm CMOS technology where the total harmonic distortion (THD) is less than 1.1%, the linearity error is also less than 3%, -3db frequency is more than 180 MHz and the voltage input range is 3 Vp-p− . Simulation results are given to verify the functionality of the proposed multiplier.

Prediction of the thermo-mechanical behavior of machine-tool spindles is essential in the reliable operation of High Speed machine tools. In particular, the performance of these High Speed spindles is dependent on their thermal behavior. The main source of heat generation in the spindle is the friction torque in angular contact ball bearings. This paper presents an effort to develop a comprehensive model of High Speed spindles that includes viable models for the mechanical and thermal behavior of its major components, i.e., bearings, shaft and housing. Spindle housing and shaft are treated as six-degree-of-freedom Timoshenko beam elements. Bearings are modeled as two-node elements with five displacements and a thermal load component at each node. Mutual interaction between the thermal and structural behavior of both spindle shaft/housing and bearings is characterized through thermal expansion and the rate of heat generation/transfer. Components are combined to form a finite element model for the thermo-mechanical analysis of spindle-bearing systems.The results of simulation for a typical spindle system are presented.

Performance of two axisymmetric air intakes are compared at conditions suitable for Mach number range from 2 to 8. First is the Busemann intake and second is the reversed isentropic nozzle. The isentropic nozzle is built by the method of characteristics. The contour of this nozzle is taken as a compression surface for the incoming flow. Performances of these two intakes are compared by comparison of both viscous and inviscid CFD calculations at Mach 6. Viscous flow calculations show that the total pressure recovery in compression section is 0. 8316 in the Busemann intake and 0. 869 in the reversed isentropic nozzle intake.

ASIC implementation of a High Speed multiplier using a High accuracy oating point logarithmic number system is reported in this paper. The most popularly used techniques for computing logarithmic calculations for digital signal processors are: Lookup table based implementation, polynomial approximation, and Taylor series expansion. But, all these techniques suer from low accuracy, due to the choice of having only lower order terms of the expanded series. In the present work, logarithmic conversion is implemented by a oating point (IEEE-754 single precision) converting methodology, thereby eliminating series expansion, which eventually results in High accuracy. The improvement in Speed, by avoidance of carry propagation, was achieved through Canonical Signed Digit Code (CSDC) implementation, while the High accuracy was achieved through an error minimization circuitry especially designed for this purpose. The functionality of these circuits was checked, and performance parameters, like propagation delay and dynamic power consumption, were calculated by spice spectre using 90 nm CMOS technology. The propagation delay and power consumption of the resulting (128 128) bit multiplier (divider) was only 93 ns and ~ 80 mW, respectively, for a layout area of ~ 25mm2. This implementation oered a signi can’t improvement in terms of accuracy, delay and power from those reported earlier.